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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Rev. 01 -- 1 February 2007 Product data sheet
1. General description
The PCA9675 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus family. The PCA9675 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus (Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts. The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The PCA9675 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. The internal Power-On Reset (POR) or software reset sequence initializes the I/Os as inputs.
2. Features
I I I I I I I I I I I I I 1 MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 16-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 400 mA Active LOW open-drain interrupt output 64 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current -40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
I Packages offered: SO24, SSOP24, QSOP24, TSSOP24, HVQFN24, DHVQFN24
3. Applications
I I I I I I I LED signs and displays Servers Industrial control PLCs Cellular telephones Gaming machines Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information Topside mark PCA9675D Package Name SO24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT137-1 SOT556-1 SOT355-1 SOT815-1 SOT616-1 Type number PCA9675D PCA9675DK PCA9675PW PCA9675BQ PCA9675BS
PCA9675DB[1] PCA9675DB SSOP24 PCA9675DK SSOP24[2] PCA9675PW TSSOP24 9675 9675
plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
[1] [2]
The PCA9675DB is a drop-in replacement (same package, footprint, pinout and software) for the PCF8575TS. Also known as QSOP24.
PCA9675_1
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Product data sheet
Rev. 01 -- 1 February 2007
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
5. Block diagram
PCA9675
INT AD0 AD1 AD2 SCL SDA INPUT FILTER I2C-BUS CONTROL SHIFT REGISTER 16 BITS I/O PORT P00 to P07 P10 to P17 INTERRUPT LOGIC LP FILTER
write pulse read pulse VDD VSS POWER-ON RESET
002aab627
Fig 1. Block diagram of PCA9675
write pulse Itrt(pu) data from Shift Register D FF CI S power-on reset D FF read pulse CI S Q Q
100 A
IOH
VDD
IOL
P00 to P07 P10 to P17
VSS
data to Shift Register
002aab631
to interrupt logic
Fig 2. Simplified schematic diagram of P00 to P17
PCA9675_1
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Product data sheet
Rev. 01 -- 1 February 2007
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
6. Pinning information
6.1 Pinning
INT AD1 AD2 P00 P01 P02 P03 P04 P05
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aab628
INT AD1 AD2 P00 P01 P02 P03 P04 P05
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aab629
PCA9675D
PCA9675PW
P06 10 P07 11 VSS 12
P06 10 P07 11 VSS 12
Fig 3. Pin configuration for SO24
Fig 4. Pin configuration for TSSOP24
INT AD1 AD2 P00 P01 P02 P03 P04 P05
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aac268
INT AD1 AD2 P00 P01 P02 P03 P04 P05
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aab815
PCA9675DK
PCA9675DB
P06 10 P07 11 VSS 12
P06 10 P07 11 VSS 12
Fig 5. Pin configuration for SSOP24 (QSOP24)
Fig 6. Pin configuration for SSOP24
PCA9675_1
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Product data sheet
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4 of 34
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
terminal 1 index area AD1 20 SDA 19 SCL 24 AD2 23 AD1 21 VDD terminal 1 index area P00 P01 P02 P03 P04 P05 1 2 3 4 5 6 P10 10 P11 11 P12 12 7 8 9 22 INT AD2 P00 P01 18 AD0 17 P17 16 P16 15 P15 14 P14 13 P13 P02 P03 P04 P05 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 P10 13
PCA9675BQ
PCA9675BS
P06 10 P07 11 VSS 12
VSS
P06
P07
1
INT
002aab630
002aac269
Transparent top view
Transparent top view
Fig 7. Pin configuration for HVQFN24
Fig 8. Pin configuration for DHVQFN24
6.2 Pin description
Table 2. Symbol Pin description Pin SO, SSOP, TSSOP, HVQFN DHVQFN INT AD1 AD2 P00 P01 P02 P03 P04 P05 P06 P07 VSS P10 P11 P12 P13 P14 P15 P16 P17 AD0
PCA9675_1
Description
1 2 3 4 5 6 7 8 9 10 11 12[1] 13 14 15 16 17 18 19 20 21
22 23 24 1 2 3 4 5 6 7 8 9[1] 10 11 12 13 14 15 16 17 18
interrupt output (active LOW) address input 1 address input 2 quasi-bidirectional I/O 00 quasi-bidirectional I/O 01 quasi-bidirectional I/O 02 quasi-bidirectional I/O 03 quasi-bidirectional I/O 04 quasi-bidirectional I/O 05 quasi-bidirectional I/O 06 quasi-bidirectional I/O 07 supply ground quasi-bidirectional I/O 10 quasi-bidirectional I/O 11 quasi-bidirectional I/O 12 quasi-bidirectional I/O 13 quasi-bidirectional I/O 14 quasi-bidirectional I/O 15 quasi-bidirectional I/O 16 quasi-bidirectional I/O 17 address input 0
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 1 February 2007
5 of 34
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Pin description ...continued Pin SO, SSOP, TSSOP, HVQFN DHVQFN Description
Table 2. Symbol
SCL SDA VDD
[1]
22 23 24
19 20 21
serial clock line input serial data line input/output supply voltage
HVQFN and DHVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 "Block diagram of PCA9675".
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9675 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 "PCA9675 address map". Remark: The General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9675 not to acknowledge. Remark: Reserved I2C-bus addresses must be used with caution since they can interfere with:
* "reserved for future use" I2C-bus addresses (0000 011, 1111 101, 1111 110,
1111 111)
* slave devices that use the 10-bit addressing scheme (1111 0xx) * High speed mode (Hs-mode) master code (0000 1xx)
slave address A6 A5 A4 A3 A2 A1 A0 R/W
programmable
002aab636
Fig 9. PCA9675 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is applied.
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Product data sheet
Rev. 01 -- 1 February 2007
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
7.1.1 Address maps
Table 3. AD2 VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD PCA9675 address map AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address (hex) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh
PCA9675_1
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Product data sheet
Rev. 01 -- 1 February 2007
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
PCA9675 address map ...continued AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address (hex) A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh E0h E2h E4h E6h E8h EAh ECh EEh
Table 3. AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA
PCA9675_1
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Product data sheet
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
7.2 Software Reset call, and Device ID addresses
Two other different addresses can be sent to the PCA9675.
* General Call address: allows to reset the PCA9675 through the I2C-bus upon
reception of the right I2C-bus sequence. See Section 7.2.1 "Software Reset" for more information.
* Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 "Device ID (PCA9675 ID field)" for more information.
R/W 0 0 0 0 0 0 0 0
002aac155
Fig 10. General Call address
1
1
1
1
1
0
0
R/W
002aab638
Fig 11. Device ID address
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address `0000 000' with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9675 device(s) acknowledge(s) after seeing the General Call address `0000 0000' (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. a. The PCA9675 acknowledges this value only. If the byte is not equal to 06h, the PCA9675 does not acknowledge it. If more than 1 byte of data is sent, the PCA9675 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9675 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed.
PCA9675_1
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Product data sheet
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
The I2C-bus master must interpret a non-acknowledge from the PCA9675 (at any time) as a `Software Reset Abort'. The PCA9675 does not initiate a reset of its registers. The unique sequence that initiates a Software Reset is described in Figure 12.
SWRST Call I2C address S 0 0 0 0 0 0 0 0 R/W acknowledge from slave(s) A 0
SWRST data = 06h 0 0 0 0 1 1 0 A P
START condition
acknowledge from slave(s)
PCA9675 is(are) reset. Registers are set to default power-up values.
002aac156
Fig 12. Software Reset sequence
7.2.2 Device ID (PCA9675 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
* 8 bits with the manufacturer name, unique per manufacturer (for example,
NXP Semiconductors).
* 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example, PCA9675 16-bit quasi-output I/O expander).
* 3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hard wired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I2C-bus address `1111 100' with the R/W bit set to 0 (write). 3. The master sends the I2C-bus slave address of the slave device it needs to identify. The LSB is a `Don't care' value. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. The master sends a Re-START command. Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID read cannot be performed. Remark: A STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID read cannot be performed. 5. The master sends the Reserved Device ID I2C-bus address `1111 100' with the R/W bit set to 1 (read). 6. The device ID read can be done, starting with the 8 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 13 part identification bits and then the 3 die revision bits (3 LSB of the third byte). 7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command.
PCA9675_1
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Product data sheet
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. Remark: If the master continues to ACK the bytes after the third byte, the PCA9675 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. For the PCA9675, the Device ID is as shown in Figure 13.
manufacturer
0
0
0
0
0
0
0
0
part identification
0
0
0
0
0
0
1
0
0
1
1
0
0
category identification
feature identification revision 0 0 0
002aab639
Fig 13. PCA9675 ID
acknowledge from one or several slave(s) device ID address S 1 1 1 1 1 0 0 0 R/W don't care A A6 A5 A4 A3 A2 A1 A0 X I2C-bus slave address of the device to be identified acknowledge from master
acknowledge from slave to be identified acknowledge from slave to be identified A 1 1 1 1 1 0 0 1 R/W A
START condition
device ID address acknowledge from master
no acknowledge from master P
M7 M6 M5 M4 M3 M2 M1 M0 A C6 C5 C4 C3 C2 C1 C0 F5 A F4 P3 P2 P1 P0 R2 R1 R0 A category identification = 0000001 revision = 000 feature identification = 001100
manufacturer name = 00000000
STOP condition
002aab663
If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a `no acknowledge'.
Fig 14. Device ID field reading
PCA9675_1
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Product data sheet
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
The PCA9675's 16 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 17). Output data is transmitted to the ports in the Write mode (see Figure 16). Every data transmission from the PCA9675 must consist of an even number of bytes, the first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third will be referred to as P07 to P00, and so on. This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the Write mode is entered. The PCA9675 acknowledges and the master sends the first data byte for P07 to P00. After the first data byte is acknowledged by the PCA9675, the second data byte P17 to P10 is sent by the master. Once again, the PCA9675 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been acknowledged by the PCA9675. The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten. The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data byte in every pair refers to Port 1 (P17 to P10). See Figure 15.
first byte 07 06 05 04 03 02 01 00 A 17 16 15
second byte 14 13 12 11 10 A
P07 P06 P05 P04 P03 P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
002aab634
Fig 15. Correlation between bits and ports
PCA9675_1
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Product data sheet
Rev. 01 -- 1 February 2007
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
SCL
1
2
3
4
5
6
7
8
9 data to port 0 data to port 1
slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W
PP PPPPP P PPPPPP A 07 06 1 04 03 02 01 00 A 17 1 15 14 13 12 11 10 A P05 acknowledge from slave P16 acknowledge from slave tv(Q) acknowledge from slave
write to port tv(Q) data A0 and B0 valid data A0 and B0 valid
data output from port P05 output voltage
P05 pull-up output current
Itrt(pu) IOH
P16 output voltage
P16 pull-up output current INT td(rst)
Itrt(pu) IOH
002aab632
Fig 16. Write mode (output)
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost.
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Product data sheet Rev. 01 -- 1 February 2007
(c) NXP B.V. 2007. All rights reserved. PCA9675_1
NXP Semiconductors
SCL
1
2
3
4
5
6
7
8
9 P0x P1x A acknowledge from master DATA 11 A acknowledge from master P0x DATA 00 A acknowledge from master P1x DATA 12 1 P
SDA S 0 1 0 0 A2 A1 A0 1 R/W acknowledge from slave read from port 0 A
DATA 00
START condition
no acknowledge from master
data into port 0
DATA 00
read from port 1
data into port 1
DATA 10
DATA 11
DATA 12
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
INT tv(D) td(rst)
002aab810
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
Fig 17. Read input port register, scenario 1
PCA9675
14 of 34
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Product data sheet Rev. 01 -- 1 February 2007
(c) NXP B.V. 2007. All rights reserved. PCA9675_1
NXP Semiconductors
SCL
1
2
3
4
5
6
7
8
9 P0x P1x A acknowledge from master DATA 10 A acknowledge from master P0x DATA 03 A acknowledge from master P1x DATA 12 1 P
SDA S 0 1 0 0 A2 A1 A0 1 R/W acknowledge from slave read from port 0 th(D) data into port 0 DATA 00 A
DATA 00
START condition
no acknowledge from master
tsu(D) DATA 01 th(D) DATA 02 DATA 03
read from port 1 tsu(D) data into port 1 DATA 10 DATA 11 DATA 12
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
INT tv(D) td(rst)
002aab811
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
Fig 18. Read input port register, scenario 2
PCA9675
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9675 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9675 registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)
The PCA9675 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 17, Figure 18, and Figure 19). This gives these chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time t(v)D the signal INT is valid. The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). The interrupt is reset in the read mode on the rising edge of the read from port pulse. During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT.
VDD
device 1
device 2
device 8
PCA9675
MICROCOMPUTER INT INT
PCA9675
PCA9675
INT
INT
002aab635
Fig 19. Application of multiple PCA9675s with interrupt
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 20).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 20. Bit transfer
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 21.)
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 21. Definition of START and STOP conditions
9.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 22).
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 22. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 23. Acknowledgement on the I2C-bus
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Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 24, P00 and P01 are inputs, and P02 to P07 are outputs. When used in this configuration, during a write, the input (P00 and P01) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to P07). During a read, the logic levels of the external devices driving the input ports (P00 and P01) and the previous written logic level to the output ports (P02 to P07) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I2C-bus.
VDD
VDD VDD
CORE PROCESSOR
SDA SCL INT
AD0 AD1 AD2
P00 P01 P02 P03 P04 P05 P06 P07
temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3
002aab812
Fig 24. Bidirectional I/O expander application
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA.
VDD
VDD
VDD
CORE PROCESSOR
SDA SCL INT
AD0 AD1 AD2
P00 P01 P02 P03 P04 P05 P06 P07
LOAD
002aab813
Fig 25. High current-drive load application
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
10.3 Differences between the PCA9675 and the PCF8575
The PCA9675 is a drop in replacement for the PCF8575 and can used without electrical or software modifications, but there is a difference in interrupt output release timing during the read operation. Write operations are identical. At the completion of each 8-bit write sequence the data is stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n then P1n again. Any write will update both read registers and clear interrupts. Read operations are identical. Both devices update the byte register with the pin data as each 8-bit read is initiated, the very first read after an address cycle corresponds to ports P0n while the second (even byte) corresponds to P1n and subsequent reads without a STOP wrap around to P0n then P1n again. During read operations, the PCA9675 interrupt output will be cleared in a byte-wise fashion as each byte is read. Reading the first byte will clear any interrupts associated with the P0n pins. This first byte read operation will have no effect on interrupts associated with changes of state on the P1n pins. Interrupts associated with the P1n pins will be cleared when the second byte is read. Reading the second byte has no effect on interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt output will clear after reading both bytes of data regardless of whether data was changed in the first byte or the second byte or both bytes.
11. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD ISS VI II IO Ptot P/out Tstg Tamb
[1]
Parameter supply voltage supply current ground supply current input voltage input current output current total power dissipation power dissipation per output storage temperature ambient temperature
Conditions
Min -0.5 VSS - 0.5 -65
Max +6 100 600 5.5 20 50[1] 600 200 +150 +85
Unit V mA mA V mA mA mW mW C C
operating
-40
Total package (maximum) output current is 600 mA.
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Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
12. Static characteristics
Table 5. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD Istb VPOR VIL VIH IOL IL Ci IOL supply voltage supply current standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level output current[2] VOL = 0.4 V VI = VDD or VSS VI = VSS VOL = 0.5 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V IOL(tot) IOH Itrt(pu) Cio(off) total LOW-level output current[2] VOL = 0.5 V; VDD = 4.5 V VOH = VSS
[3]
Parameter
Conditions
Min 2.3
Typ 250 2.5 1.6 5 28 35 42 -102 -1.0 9
Max 5.5 500 10 2.0
Unit V A A V
Operating mode; no load; VI = VDD or VSS; fSCL = 1 MHz Standby mode; no load; VI = VDD or VSS
[1]
-0.5 0.7VDD 20 -1 12 17 25 -30 -0.5 -
Input SCL; input/output SDA +0.3VDD V 5.5 +1 10 400 -300 10 V mA A pF mA mA mA mA A mA pF
I/Os; P00 to P07 and P10 to P17
HIGH-level output current off-state input/output capacitance LOW-level output current output capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
transient boosted pull-up current VOH = VSS; see Figure 16
Interrupt INT IOL Co VIL VIH ILI Ci
[1] [2] [3]
VOL = 0.4 V
6 -0.5 0.7VDD -1 -
2.1 2.4
5
mA pF
Inputs AD0, AD1, AD2 +0.3VDD V 5.5 +1 5 V A pF
The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD). Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits. The value is not tested, but verified on sampling basis.
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
13. Dynamic characteristics
Table 6. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Standard mode Fast mode I2C-bus Fast mode Plus Unit I2C-bus I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid time acknowledge time [1] data valid time[2] data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter [6] data output valid time data input setup time data input hold time data input valid time reset delay time
[4][5]
Max 100 3.45 300 1000 50
Min 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb [3] 20 + 0.1Cb [3] -
Max 400 0.9 300 300 50
Min 0 0.5 0.26 0.26 0.26 0 0.05 50 50 0.5 0.26 -
Max 1000 0.45 450 120 120 50 kHz s s s s ns s ns ns s s ns ns ns
0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -
Port timing; CL 100 pF (see Figure 16 and Figure 17) tv(Q) tsu(D) th(D) tv(D) td(rst)
[1] [2] [3] [4] [5]
0 4 -
4 4 4
0 4 -
4 4 4
0 4 -
4 4 4
s s s s s
Interrupt timing; CL 100 pF (see Figure 16 and Figure 17)
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL's falling edge. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(c) NXP B.V. 2007. All rights reserved.
[6]
PCA9675_1
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 26. I2C-bus timing diagram
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
14. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 27. Package outline SOT137-1 (SO24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 28. Package outline SOT340-1 (SSOP24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm
SOT556-1
D
E
A X
c y HE vM A
Z 24 13
A2 A1 (A 3) Lp L 1 e bp 12 wM detail X
A
0
2.5 scale
5 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm inches A max. 1.73 0.068 A1 0.25 0.10 A2 1.55 1.40 A3 0.25 0.01 bp 0.31 0.20 c 0.25 0.18 D(1) 8.8 8.6 E(1) 4.0 3.8 e 0.635 HE 6.2 5.8 L 1 Lp 0.89 0.41 v 0.25 0.01 w 0.18 y 0.1 Z(1) 1.05 0.66 0.040 0.026 8 o 0 8o o 0
o
0.0098 0.061 0.0040 0.055
0.012 0.0098 0.344 0.157 0.244 0.035 0.025 0.041 0.008 0.0075 0.337 0.150 0.228 0.016
0.007 0.004
Note 1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included. OUTLINE VERSION SOT556-1 REFERENCES IEC JEDEC MO-137 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 29. Package outline SOT556-1 (SSOP24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 30. Package outline SOT355-1 (TSSOP24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
E
A
A1 c
detail X terminal 1 index area C terminal 1 index area 2 L 12 e1 e b 11 vMCAB wM C y1 C y
1
Eh
e2
24 13
23 Dh 0
14 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.6 5.4 Dh 4.25 3.95 E (1) 3.6 3.4 Eh 2.25 1.95 e 0.5 e1 4.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT815-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION
ISSUE DATE 03-04-29
Fig 31. Package outline SOT815-1 (DHVQFN24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 e y1 C y
e 7 L 6
Eh
1/2 e
e2
1
18
terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 32. Package outline SOT616-1 (HVQFN24)
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 33) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8
Table 7. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 8. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 33.
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PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 33. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 9. Acronym CDM CMOS ESD GPIO HBM LED ID LSB MM MSB PLC RAID Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge General Purpose Input/Output Human Body Model Light Emitting Diode Identification Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Redundant Array of Independent Disks
18. Revision history
Table 10. Revision history Release date 20070201 Data sheet status Product data sheet Change notice Supersedes Document ID PCA9675_1
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NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PCA9675_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 1 February 2007
33 of 34
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
21. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.2.1 7.2.2 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.1.1 9.2 9.3 10 10.1 10.2 10.3 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software Reset call, and Device ID addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device ID (PCA9675 ID field) . . . . . . . . . . . . . 10 I/O programming . . . . . . . . . . . . . . . . . . . . . . . 12 Quasi-bidirectional I/O architecture . . . . . . . . 12 Writing to the port (Output mode) . . . . . . . . . . 12 Reading from a port (Input mode) . . . . . . . . . 13 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 16 Characteristics of the I2C-bus. . . . . . . . . . . . . 17 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 START and STOP conditions . . . . . . . . . . . . . 17 System configuration . . . . . . . . . . . . . . . . . . . 17 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application design-in information . . . . . . . . . 19 Bidirectional I/O expander applications . . . . . 19 High current-drive load applications . . . . . . . . 19 Differences between the PCA9675 and the PCF8575. . . . . . . . . . . . . . . . . . . . . . . . . . 20 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 Static characteristics. . . . . . . . . . . . . . . . . . . . 21 Dynamic characteristics . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Handling information. . . . . . . . . . . . . . . . . . . . 30 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Introduction to soldering . . . . . . . . . . . . . . . . . 30 Wave and reflow soldering . . . . . . . . . . . . . . . 30 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 30 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 Legal information. . . . . . . . . . . . . . . . . . . . . . . 33 19.1 19.2 19.3 19.4 20 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 33 33 34
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 February 2007 Document identifier: PCA9675_1

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